Semiconductor devices may include interconnection structures for electrically connecting electronic components (e.g., transistors, capacitors and resistances) to form desired electric circuits. The interconnection structures may include a plurality of conductive interconnections, also known as “traces.” For example, an interconnection structure may include lower traces arranged on a lower metallization layer of the semiconductor substrate, upper traces arranged on an upper metallization layer above the lower traces, and conductive vias in a region between the upper and lower metallization layers that electrically connect the lower traces on the lower layer to the upper traces on the upper layer. Conventional interconnection structures are described in “Silicon Processing for the VLSI Era: Volume 2—Process Integration”, pages 84–296 of Chapter 3 and 4, by Stanley Wolf, published on 1990 edition by Lattice Press.
FIG. 1 is a flowchart illustrating conventional operations for designing, fabricating and revising interconnection structures in semiconductor devices.
Referring now to FIG. 1, a circuit layout for a semiconductor device is determined (block S1), and one or more photomasks are fabricated based on the determined circuit layout (block S2). The circuit layout may include the routing of traces on each layer of a semiconductor substrate. The semiconductor device is then fabricated using the photomask(s) (block S3). More specifically, a photolithography process is performed to copy the determined circuit layout from each photomask to a layer of the semiconductor substrate. The fabricated semiconductor device is then examined for quality (block S4). Devices passing a predetermined examination standard may be sold. If technical defects are found, a request may be made to revise the arrangement and/or routing of the traces so as to correct the defects. The revision (block S5) may also be performed to improve the performance of the semiconductor device.
FIGS. 2A and 2B are schematic diagrams illustrating conventional methods of revising interconnection structures in semiconductor devices.
As shown in FIG. 2A, lower traces 10 (on a lower metallization layer of the substrate) are connected to upper traces 30 (on an upper metallization layer of the substrate) by conductive vias 20 arranged in a predetermined region of the semiconductor substrate between the upper and lower layers. In particular, FIG. 2A illustrates an embodiment where first and second lower traces 11 and 12 are respectively connected to one 31 of the upper traces 30 by first and second vias 21 and 22. In this embodiment, the upper traces 30 include first to sixth upper traces 31 to 36.
Referring now to FIG. 2B, if the layout is revised such that a second one 12′ of the lower traces 10′ is to be electrically connected to a seventh one 37 of the upper traces 30′, it may be necessary to add the seventh upper trace 37, extend the second lower trace 12′ on the lower layer to vertically overlap with the seventh upper trace 37 on the upper layer, and move the via 22′ to the overlapping position. As such, the routing of the lower traces 10′, the vias 20′ and the upper traces 30′ may require revision. If such a revision is requested, it may be necessary to fabricate a new photomask for each of the affected layers, which may increase the costs of device fabrication.